Latent Damage and Reliability in Semiconductor Devices
Senior Design Project for Fall 2015 and Spring 2016
This project will focus on a study of latent damage in integrated circuits and its corresponding effects on reliability. Latent damage is damage that has been introduced but can not be detected or observed with existing nondestructive methods. Some scholars claim that latent damage does not exist but others have provided measurements that show experimentally that latent damage can be introduced in some circuit structures.
Common causes of damage in integrated circuits are Electrostatic Discharge (ESD) events associated with static noise in the environment and short high-voltage power supply transients caused by lightning strikes on power lines. When some integrated circuits in a system are destroyed by such events, a standard repair approach is to replace non-functioning modules or components to restore system performance. But questions about the reliability of the repaired system remain if latent damage exists in the properly functioning modules and components that were not replaced.
In this project, an experimental study of the effects of stress near the failure limit on standard semiconductor devices will be made to assess whether latent damage occurs and, if it does, to assess the impact on reliability. Stress will be introduced with short-duration high voltage spikes applied to appropriate pins on standard commercial integrated circuits that are just below the failure level. Accelerated lifetime tests will then be conducted with stressed parts and unstressed parts to assess whether the stress has any significant impact on lifetime and reliability. An industry standard test oven is available for conducting accelerated lifetime tests.
Though this is a research project focusing on latent damage, there are considerable job opportunities in industry for engineers focusing on fault diagnosis and reliability of semiconductor devices.